1. Field of the Invention
The present invention relates to a semiconductor device and its fabrication method and, more particularly, to a semiconductor device which avoids latch-up by reducing the shunting resistance between the emitter and base of a parasitic bipolar transistor and the current gain of the base, and its fabrication method.
2. Discussion of Related Art
Latch-up, a generic problem associated with complementary metal oxide semiconductor (hereinafter called CMOS) structures causes undesirable conduction phenomena to occur in the parasitic NPN and PNP bipolar transistors inherent in CMOS structure, for example, malfunction or destruction of the devices due to over-current such as transient pulses.
In scaling down of CMOS integrated circuits, the closer spacing between semiconductor regions, especially, P and N junctions increases the current gain of the parasitic NPN and PNP bipolar transistors and turns on the parasitic SCR (Silicon Controlled Rectifier) structure and latch it into conductivity state. Namely, latch-up occurs.
FIG. 1 is a cross-sectional view of the related art semiconductor device.
Referring to FIG. 1, the related art semiconductor device, e.g., CMOS inverter circuit has P well 22 and N well 21 formed in a semiconductor substrate 11. A field oxide layer 13 is formed to define the active and isolation regions of the device. A heavily doped P type regions 27 and 28 are formed in the N well 21 by using a first gate 37 overlying a gate insulating layer 23 as a mask. A heavily doped N type region of N-well contact 30 is then formed at a predetermined portion in the N well 21. The heavily doped P type regions 28 and 27 become source and drain regions of P channel FET, respectively. A heavily doped N type regions 25 and 26 are formed in the P well 22 by using a second gate 38 overlying the gate insulating layer 23 as a mask. A heavily doped P type region of P-well contact region 29 is formed at a predetermined portion in the P well 22. The heavily doped N type regions 25 and 26 become source and drain regions of N channel FET, respectively.
In the CMOS inverter circuit 39 having the above-described structure, the P-well contact region 29 and the source region 25 of N channel FET are connected to a ground terminal V.sub.ss, while the source region 28 of P channel FET and the N-well contact region 30 are connected to a power source V.sub.DD. The first and second gates 37 and 38 are connected to an input terminal V.sub.IN, and the drains 26 and 27 of N channel and P channel FETs being connected to an output terminal V.sub.OUT.
In operation, a signal applied to the input terminal V.sub.IN at logic high voltage level will cause the N channel FET to turn on. At the same time, the P channel FET is turned off, such that substantially no current flows between the drain and source regions 27 and 28 of P channel FET.
The output terminal V.sub.OUT connected to the drain regions 26 and 27 is therefore pulled to the lower supply voltage V.sub.SS through the N channel FET. The CMOS inverter circuit 39 has thus inverted the input logic high voltage level to an output logic low voltage level.
As shown in FIG. 1, the CMOS semiconductor device 39 includes two parasitic bipolar transistors 35 and 36. The transistor 35 is an NPN bipolar transistor with source region 25 of N channel FET forming its emitter, the P well 22 forming its base and N well 21 forming its collector. The transistor 36 is a PNP bipolar transistor with source region 28 of P channel FET forming its emitter, the N well 21 forming its base and the P well 22 forming its collector.
In normal operation of the CMOS inverter circuit 39, the transistors 35 and 36 are off and the emitter-base PN junction thereof conducts only a minimal leakage current. However, a voltage drop of over 0.6 volts occurs at the ground terminal Vss momentarily due to an electrostatic discharge (ESD) voltage spike inadvertently applied to the device. This voltage drop causes electrons to be injected from the source region 25 of N channel FET into P well 22, then the NPN transistor 35 is turned on and the electrons reach the N well 21.
In a case where the electron current(I) and the resistance(R) between N-well contact region 30 and the source region 28 of P channel FET are high sufficiently, a voltage drop of about 0.6 volts also occurs in a small critical current or N-well current, turning the transistor 36 on. This drop in potential causes holes to be injected into the N well 21 from the source region 28 of P channel PET and reaches the P well 22.
Furthermore, when the resistance between P-well contact region 29 and the source region 25 of N channel FET is high sufficiently, a voltage drop of about 0.6 volts occurs in a small critical current or P-well current to turn the transistor 35 on. This voltage drop causes electrons to be injected into the P well 22 from the source region 25. This electron current adds to the initial current and strengthens the positive feed back between PNP and NPN transistors 36 and 35, respectively, which thus leads to the latch-up condition.
The related art CMOS inverter circuit 39 is, however, disadvantageous in that a voltage drop capable of turning on the bipolar transistors 36 and 35 occurs at a small critical current and the latch-up occurs in a case of the sufficiently high resistance between the N-well contact region 30 and the source region 28 of P channel FET or between the P-well contact region 29 and the source region 25 of N channel FET.